Glitch Mitigation in Switched Reactance Phase Shifters

ABSTRACT

A phase shifter cell and multiple coupled phase shifter cells that mitigate signal glitches arising from phase state changes by a combination of design architecture and control signal timing. Specifically, one or more of the following three concepts are employed to mitigate insertion loss glitches and control phase behavior during phase state transitions: the timing of switching for each switched half-cell (e.g., including series and/or shunt reactance elements, such as inductors and/or capacitors) within a phase shifter cell is controlled in such a way that the reactance elements do not all switch at the same time; use of a “make before break” timing scheme for combination or “multi-state” phase shifter cells; and/or arranging the timing of each phase shifter cell in a set of multiple coupled phase shifter cells such that the individual cells do not all switch at the same time.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No.15/017,433, filed on Feb. 5, 2016, entitled “Low Loss Multi-State PhaseShifter” [ATTY DOCKET No. PER-156-PAP], assigned to the assignee of thepresent invention, the contents of which are hereby incorporated byreference.

BACKGROUND (1) Technical Field

This invention generally relates to electronic circuits, and morespecifically to digital-step phase shifter circuits.

(2) Background

Electronic phase shifter circuits are used to change the transmissionphase angle of a signal, and are commonly used to phase shift radiofrequency (RF) signals. An RF phase shifter circuit may be implementedwith different configurations of reactance elements (e.g., inductors andcapacitors) and other components (e.g., resistors, switches, etc.). RFphase shifter circuits may be used for applications such as in-phasediscriminators, beam forming networks, power dividers, linearization ofpower amplifiers, and phased array antennas, to name a few.

For many applications, it may be useful to serially-couple multiplephase shifter cells of the same or different phase shift values. Suchphase shifter circuits may be digitally controlled and thus provide adiscrete set of phase shift states or steps that are selected by abinary control word, directly or after decoding. Such phase shiftercircuits may be binary-coded, thermometer coded, or a hybrid combinationof the two types.

FIG. 1 is a block diagram of a conventional prior art 90° phase shiftercell 100. Two ports, P1, P2, either of which may be an input port to thephase shifter cell 100 for an RF signal or an output port for the phaseshifter cell 100, are coupled to a −45° low pass filter (LPF) circuit102 and a +45° high pass filter (HPF) circuit 104. The serially-coupledLPF circuit 102 and the HPF circuit 104 may also be considered to be“half-cells”. A half-cell is considered to be in an inactive, decoupled,or OFF state when it is configured to allow an applied signal to passthrough the half-cell essentially unmodified, and in an active, coupled,or ON state when it is configured to phase shift an applied signal.

In the illustrated example, the LPF circuit 102 has a conventionalpi-type configuration, in which an inductor L_(LPF) reactance element isseries-coupled between ports P1 and P2, and in parallel with athrough-path switch M1 controlled by a signal S1. Bracketing shuntcapacitors C_(LPF) may be coupled between respective ports P1 and P2 anda common potential (e.g., circuit ground) by corresponding switches M2controlled by a signal S2.

In the illustrated example, the HPF circuit 104 has a conventionalT-type configuration, in which a pair of capacitor C_(HPF) reactanceelements are series-coupled between ports P1 and P2, and in parallelwith corresponding through-path switches M3 controlled by a signal S3. Ashunt inductor L_(HPF) may be coupled between a junction point betweenthe pair of capacitor C_(HPF) reactance elements and the commonpotential by a switch M4 controlled by a signal S4.

FIG. 2 is a timing diagram of conventional control signals for the phaseshifter cell 100 shown in FIG. 1. In operation, the state of the controlsignals S1-S4 for the switches M1-M4 are controlled by a master controlsignal V_(C). In this example, each switch M1-M4 is implemented as afield-effect transistor (FET) that becomes conductive (“ON”) when itscorresponding control signal is high, and non-conductive (“OFF”) whenits corresponding control signal is low (of course, the reverse logiccould be implemented as well by suitable changes in components andcontrol signals).

When V_(C) is at a logic high, the phase shifter cell 100 is in a +45°high pass state; conversely, when V_(C) is at a logic low, the phaseshifter cell 100 is in a −45° low pass state. In the high pass state, S1is high, S3 is low, S2 is low, and S4 is high. In the low pass state, S1is low, S3 is high, S2 is high, and S4 is low. Thus, S1 and S3 arecomplementary with respect to each other, S2 and S4 are complementarywith respect to each other, S1 and S2 are complementary with respect toeach other, and S3 and S4 are complementary with respect to each other.

In this example, before time point “A”, the phase shifter cell 100 is ina +45° high pass state: signals applied at port P1 pass through theinactive LPF circuit 102 via ON switch M1 (since S1 is high and S2 islow, the applied signals simply pass through the LPF circuit 102) andare phase shifted by the active HPF circuit 104 (since S3 is low and S4is high). After time point “A”, the phase shifter cell 100 is in a −45°low pass state: signals applied at port P1 are phase shifted by theactive LPF circuit 102 (since S1 is low and S2 is high) and pass throughthe inactive HPF circuit 104 via ON switches M3 (since S3 is high and S4is low, the applied signals simply pass through the HPF circuit 104).The logic state of V_(C), and hence of the control signals S1-S2, isreversed to shift back to a +45° phase shift from a −45° phase shift.

A problem of the phase shifter cell 100 shown in FIG. 1 and otherconventional phase shifter circuits (whether binary, thermometer, orhybrid coded) is that switching phase states results in undesirable RFswitching transients (“glitches”) from the switches M1-M4 during theconcurrent transitions of the control signals S1-S4. The problem iscompounded if multiple phase shifter cells 100 change phase shift stateat the same time. Such glitches can cause significant variations ininsertion loss, as well as extreme changes in the actual insertionphase.

Accordingly, there is a need for a phase shifter cell and for multiplecoupled phase shifter cells that mitigate glitches arising from phasestate changes. The present invention addresses this need.

SUMMARY OF THE INVENTION

The present invention encompasses a phase shifter cell and multiplecoupled phase shifter cells that mitigate glitches arising from phasestate changes. By understanding the vector impact of the individualphase shifter cell as it transitions, and of the entire phase shifterarchitecture, the total insertion loss glitch can be maintained to lessthan 1 dB and the phase transition made to be monotonic in itstransition behavior.

These two behaviors are achieved by a combination of design architectureand control signal timing. Specifically, one or more of the followingthree concepts are employed to mitigate insertion loss glitches andcontrol phase behavior during phase state transitions:

-   -   The timing of switching for each switched half-cell (e.g.,        including series and/or shunt reactance elements, such as        inductors and/or capacitors) within a phase shifter cell is        controlled in such a way that the reactance elements do not all        switch (either ON or OFF) at the same time;    -   Use of a “make before break” timing scheme for combination or        “multi-state” phase shifter cells; and/or    -   Arranging the timing of each phase shifter cell (or “bit”) in a        set of multiple coupled phase shifter cells such that the        individual cells do not all switch (either ON or OFF) at the        same time.

The details of one or more embodiments of the invention are set forth inthe accompanying drawings and the description below. Other features,objects, and advantages of the invention will be apparent from thedescription and drawings, and from the claims.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional prior art 90° phase shiftercell.

FIG. 2 is a timing diagram of conventional control signals for the phaseshifter cell shown in FIG. 1.

FIG. 3 is a timing diagram of an improved timing scheme for controlsignals for a phase shifter cell such as the type shown in FIG. 1.

FIG. 4A is a block diagram of one control signal generation circuit thatmay be used to generate the control signals shown in FIG. 3.

FIG. 4B is a block diagram and associated timing diagram of oneembodiment of a state dependent delay circuit.

FIG. 5A is a graph of monotonic phase transition behavior for asimulation of one embodiment of a phase shifter cell 100 switched inaccordance with the control signals shown in FIG. 3.

FIG. 5B is a graph of amplitude glitches versus time for a simulation ofone embodiment of a phase shifter cell switched in accordance with thecontrol signals shown in FIG. 3.

FIG. 5C is a graph of amplitude glitches versus time for a simulation ofa prior art embodiment of a concurrently-switched phase shifter cell.

FIG. 5D is a graph of monotonic phase transition behavior for asimulation of one embodiment of a phase shifter cell having dynamicallyswitched reactances.

FIGS. 6A-6C are block diagrams of a multi-state phase shifter cell inthree different switch states.

FIG. 6D is a block diagram of one embodiment of a timing control circuitthat may be used to control a multi-state phase shifter cell having foursignal paths in a Type 1 or Type 2 configuration, controlled by controlsignals S0-S3, respectively.

FIG. 6E is a block diagram of one embodiment of a timing control circuitthat may be used to control a multi-state phase shifter cell havingthree signal paths in a Type 3 configuration (e.g., −90°, 0°, and +90°phase shifters), controlled by control signals S0-S2, respectively.

FIG. 7 is block diagram of an enhanced phase shifter cell thatincorporates a control signal generation circuit.

FIG. 8 is a block diagram of a first embodiment of multiple coupledphase shifter cells that provide a selectable amount of phase shift toan applied signal.

FIG. 9 is a block diagram of a second embodiment of multiple coupledphase shifter cells that provide a selectable amount of phase shift toan applied signal.

FIG. 10A is a graph of amplitude glitches versus time for a simulationof the multiple coupled phase shifter cells shown in FIG. 9, for aworst-case scenario.

FIG. 10B is a graph of amplitude glitches versus time for a simulationof multiple coupled prior art phase shifter cells concurrently switchedin a worst-case scenario.

FIG. 11 is a process chart showing a method for mitigating signaltransients arising from phase state changes in a phase shifter cellhaving at least two phase shift states and a through-path state.

FIG. 12 is a process chart showing a method for mitigating signaltransients arising from phase state changes in a phase shifter cellhaving at least two phase shift states defined by two or more seriesreactances and two or more shunt reactances.

FIG. 13 is a process chart showing a method for mitigating signaltransients arising from phase state changes in a phase shifter cellhaving at least two series-coupled selectable half-cells, eachselectable half-cell having an active phase shifting state and aninactive decoupled state.

FIG. 14 is a process chart showing a method for mitigating signaltransients arising from phase state changes in a phase shifter cellincluding at least two selectable signal paths, each selectable signalpath having an active state and an inactive state.

FIG. 15 is a process chart showing a method for mitigating signaltransients arising from phase state changes in a phase shifter cellincluding at least two selectable signal paths and a selectablereference path, each selectable signal path having an active state andan inactive state.

FIG. 16 is a process chart showing a method for mitigating signaltransients arising from phase state changes in a plurality ofseries-coupled phase shifter cells.

Like reference numbers and designations in the various drawings indicatelike elements.

DETAILED DESCRIPTION OF THE INVENTION

The present invention encompasses a phase shifter cell and multiplecoupled phase shifter cells that mitigate glitches arising from phasestate changes. By understanding the vector impact of the individualphase shifter cell as it transitions, and of the entire phase shifterarchitecture, the total insertion loss glitch can be maintained to lessthan 1 dB and the phase transition made to be monotonic in itstransition behavior.

These two behaviors are achieved by a combination of design architectureand control signal timing. Specifically, one or more of the followingthree concepts are employed to mitigate insertion loss glitches andcontrol phase behavior during phase state transitions:

-   -   The timing of switching for each switched half-cell (e.g.,        including series and/or shunt reactance elements, such as        inductors and/or capacitors) within a phase shifter cell is        controlled in such a way that the reactance elements do not all        switch (either ON or OFF) at the same time;    -   Use of a “make before break” timing scheme for combination or        “multi-state” phase shifter cells; and/or    -   Arranging the timing of each phase shifter cell (or “bit”) in a        set of multiple coupled phase shifter cells such that the        individual cells do not all switch (either ON or OFF) at the        same time.

Switched Reactance Step-Wise Through-Path Phase Shifter Cell

In a phase shifter cell such as the type shown in FIG. 1, the degree ofshift may be varied by changing the values and/or number of reactanceelements within the phase shifter cell. Further, while pi-type andT-type configurations may be quite useful for the serially-coupledhalf-cells, other circuit configurations may be used to provideselectable phase states, including L-pad and bridged-T type phaseshifter circuits. Accordingly, this disclosure is not limited to thespecific phase shifter cell shown in FIG. 1.

FIG. 3 is a timing diagram of an improved timing scheme for controlsignals for a phase shifter cell such as the type shown in FIG. 1. Inthis embodiment, the aim is to transition control signals S1-S4 smoothlytransition in a step-wise fashion from a “high pass state” to a distinct“through-path state” and then to a “low pass state”, and vice versa.Switching to a distinct intermediate “through-path state” makes surethat the phase transition is also smooth (e.g., from +45° to 0°, andthen from 0° degree to)−45°.

As shown in FIG. 3, when the control voltage V_(C) transitions from highto low at time point “A”, a sequence of transitions occurs for controlsignals S1-S4. In this particular example, the control signals S1-S4 donot change immediately at time point “A”, but only begin to change afteran optional “cell delay” time expires at time point “B” (for reasonsdiscussed below with respect to FIGS. 8 and 9). Just before time point“A”, the LPF circuit 102 is inactive (since S1 is high and S2 is low,applied signals simply pass through the LPF circuit 102) and the HPFcircuit 104 is active (since S3 is low and S4 is high). At delayed timepoint “B”, S3 is changed from low to high, which makes switches M3conductive, thus enabling the through-path of the high pass filter 104.Accordingly, signals applied at port P1 simply pass through without anyappreciable phase shift (ideally, no phase shift) to port P2. The phaseshifter cell 100 has thus transitioned from a “high pass state” to a“through-path state”.

In this example, at time point “C”, delayed a selected amount of timeafter time point “B”, S2 is changed from low to high and S4 is changedfrom high to low, in a complementary fashion; however, other embodimentsmay separate the sequencing times for S2 and S4, or provide overlap ofsequencing for S2 and S4. The phase shifter cell 100 is still in a“through-path state”, since switches M1 and M3 are in a conductivestate, thus bypassing L_(LPF) and C_(HPF), respectively, but is nowconfigured to transition to the “low pass state”. At time point “D”,delayed a selected amount of time after time point “C”, S1 is changedfrom high to low, thus activating the LPF circuit 102; the HPF circuit104 is still inactive, since S3 is already high. The phase shifter cell100 has thus transitioned from the “through-path state” to a “low passstate”.

If the control voltage V_(C) transitions from low to high, the delaysequence for transitioning from a “low pass state” to a “through-pathstate” and then to a “high pass state” would be: at time point “B”, S1changes low to high; at time point “C”, S2 changes from high to low andS4 changes from low to high; and at time point “D”, S3 changes from highto low. As noted above, the sequencing of S2 and S4 need not becomplementary; other embodiments may separate the sequencing times forS2 and S4, or provide overlap of sequencing for S2 and S4.

The improved timing scheme for control signals for a phase shifter cellhaving first and second phase shifter half-cell circuits may besummarized as shown in TABLE 1 (bolding indicates a change in switchstate). Note that from the point of view of the half-cells, thisswitching scheme could be characterized as “break before make”, sinceeach half-cell is set to a through-path state between switching toopposite active states.

TABLE 1 1^(st) Phase Shifter Half-Cell 2^(nd) Phase Shifter Half-CellSeries Series Reactance Sw Shunt Sw Reactance Sw Shunt Sw Initial StateON OFF OFF ON 1^(st) transition ON OFF ON ON 2^(nd) transition ON ON ONOFF 3^(rd) transition OFF ON ON OFF

FIG. 4A is a block diagram of one control signal generation circuit 400that may be used to generate the control signals shown in FIG. 3. In theillustrated embodiment, a cell delay circuit 402 is configured toreceive the master control signal V_(C). The cell delay circuit 402provides a selectable amount of delay after a state change for V_(C)(low to high, or high to low) before passing on the applied statechange. The output of the cell delay circuit 402 is coupled to an HPdelay circuit 404 (which generates control signal S3), to a shunt delaycircuit 406 (which generates complementary control signals S2 and S4),and through an inverting input to an LP delay circuit 408 (whichgenerates control signal S1).

In the illustrated embodiment, the HP delay circuit 404 and the LP delaycircuit 408 are state dependent, meaning that a delay is generated whenthe input to those circuits transitions from low to high, and no delayis generated when the input to those circuits transitions from high tolow. For example, during a transition from +45° to 0°, and then from 0°degree to −45°, the transition for V_(C) is from high to low, making theinverted V_(C) input to the LP delay circuit 408 transition from low tohigh; the LP delay circuit 408 output will therefore be delayed.Conversely, the V_(C) input to the HP delay circuit 404 transitions fromhigh to low; the HP delay circuit 404 will therefore not be delayed.

FIG. 4B is a block diagram and associated timing diagram of oneembodiment of a state dependent delay circuit 450. A low-to-high signalapplied at the In port to a conventional delay circuit 452 will bedelayed for a selected amount of time and then propagated through to theA input of an AND gate 454. The B input to the AND gate 454 is thenon-delayed low-to-high signal. Only after the delay imposed by thedelay circuit 452 will the A and B inputs to the AND gate 454 be high,and thus the output of the AND gate 454 will be a delayed replica of thelow-to-high signal. Conversely, if a high-to-low signal is applied atthe In port, the B input to the AND gate 454 will be instantly lowregardless of the operation of the delay circuit 452, and thus theoutput of the AND gate 454 will be a non-delayed replica of thehigh-to-low signal. The timing diagram in FIG. 4B reflects the statedependent delay behavior of the circuit 450. Of course, the oppositebehavior, delaying only high-to-low input signals, may be achieved byinverting the signal applied to the In port.

The delay circuits shown in FIG. 4A and FIG. 4B may be implemented asconventional analog, digital, or hybrid analog/digital circuits, and maybe edge or level triggered. Not shown in FIG. 4A or FIG. 4B are buffercircuits that may be coupled to the output of one or more delay circuits402-210 for current driving, isolation, and/or other purposes.

For all of the delay circuits shown in FIG. 4A, the amount of delay maybe fixed at the time of manufacture (such as by application of one ormore mask layers or “blowing” fusible links), or set under programcontrol that supplies one or more Program Bits to select a delay period(for example, as shown in FIG. 4A for the cell delay circuit 402). SuchProgram Bits may be provided from look-up tables external or internal toan integrated circuit that includes the control signal generationcircuit 400, or by externally supplied control signals supplied, forexample, through dedicated pins or through a bus interface (such as thewell-known Serial Peripheral Interface bus or one of the interfacesspecified by the Mobile Industry Processor Interface Alliance), or byany other convenient means. In some embodiments, some of the delaycircuits shown in FIG. 4A or FIG. 4B may have a delay time fixed at thetime of manufacture, while others of the delay circuits may have aprogrammable delay time. For example, it may be useful to make the delaytime of the cell delay circuit 402 programmable, but have fixed delaytimes for the other delay circuits 404-408.

The effect of controlling switch transitions within a phase shifter cellin accordance with the present invention has striking advantages. Forexample, FIG. 5A is a graph 500 of monotonic phase transition behaviorfor a simulation of one embodiment of a phase shifter cell 100 switchedin accordance with the control signals shown in FIG. 3. FIG. 5B is agraph 550 of amplitude glitches versus time for a simulation of oneembodiment of a phase shifter cell 100 switched in accordance with thecontrol signals shown in FIG. 3. In this particular example, atransition is made from a low pass state (−45° phase shift) to a highpass state (+45° phase shift). In the illustrated embodiment, a firstglitch event at time “B” corresponds to the state change of the seriesreactance element switch M1 under the control of S1. A second glitchevent at time “C” corresponds to the switching of the shunt switches M2,M4 under the control of S2 and S4, respectively; the switch statechanges and settling time for their respective shunt circuits may notoccur at exactly the same time, hence the spacing that may occur betweencorresponding glitches. A third glitch event at time “D” corresponds tothe state change of the series reactance element switches M3 under thecontrol of S3. The reverse transition from a high pass state (+45° phaseshift) to a low pass state (−45° phase shift) would look similar, butwith the switching of M1-M4—and hence the glitch order and monotonicphase transition behavior—reversed.

The graph 500 of FIG. 5A illustrates that the phase transition behaviorof a phase shifter cell 100 switched in accordance with the controlsignals shown in FIG. 3 is essentially monotonic with state changes. Asillustrated in FIG. 5B, spacing the transition states of the switchesM1-M4 and transitioning from a “high pass state” to a “through-pathstate” and then to a “low pass state” (or vice versa) results in spacingout the glitches caused by each individual reactance state change. Inthe simulated embodiment, the amplitude of the largest glitch was about−2.4 dB. This is in contrast to the prior art, where switching of all ofthe switches M1-M4 at essentially the same time, or even random switchtiming, would result in a much larger glitch in amplitude. For example,FIG. 5C is a graph 560 of amplitude glitches versus time for asimulation of a prior art embodiment of a concurrently-switched phaseshifter cell. Concurrent switching of all switches M1-M4 for the samesimulated embodiment exhibited maximum amplitude glitch as high as about10 dB at time “X” (a secondary glitch at time “Y” results because, evenwith a “concurrent” switching control signal, individual transistors mayhave different switch response times). The phase glitch also can beexcessive, and in one model of a prior art configuration was as much as300° of positive glitch.

Note that the timing of switching for switches M2 and M4 can becontrolled more exactly as needed—coincident, separated, oroverlapped—but was not necessary in this example in light of inherentdifferences in the respective switch and signal response time. However,more exact control of the timing of switching of M2 and M4 may beimportant if the associated shunt reactances may interact in an adversemanner (see further discussion below).

Switched Reactance Dynamic Through-Path Phase Shifter Cell

In the switched reactance step-wise through-path phase shifter cellembodiment described above, there is a distinct transition to athrough-path state when transitioning from a “high pass state” to a “lowpass state”, and vice versa. However, in the more general case, glitchreduction within a phase shifter cell can be achieved by controlling thephase shifter cell in such a way that the reactance elements do not allswitch at the same time. More specifically, the sum of the shuntreactances and the series reactances is minimized as the correspondingphase shifter cell switches change state. Thus, instead of two phasestates and a distinct through state, the sequencing times of theswitches within a phase shifter cell (including phase shifter cells morecomplex than those shown in FIG. 1) can be dynamically and concurrentlycontrolled to comply with the following operational rule set whentransitioning from a “high pass state” to a “low pass state”, and viceversa:

-   -   the sum of the series reactances (exact or normalized) is kept        progressing monotonically while transitioning;    -   the sum of the shunt reactances (exact or normalized) is kept        progressing monotonically (but in the opposite direction from        the series reactances) while transitioning; and    -   the sum of the normalized series (x/Zo) and shunt reactances        (Zo/x) is minimized (i.e., made as close to zero as reasonably        needed for a particular application).

Note that reversing the first two steps above results in similarbehavior: the sum of the shunt reactances (exact or normalized) is keptprogressing monotonically while transitioning, then the sum of theseries reactances (exact or normalized) is kept progressingmonotonically (but in the opposite direction from the shunt reactances)while transitioning.

In embodiments of such a phase shifter cell, the series and shuntswitches (e.g., S1-S4 in FIG. 1) are calibrated such that they may bedynamically and concurrently controlled to comply with the operationalrule set above. Thus, the LPF circuit 102 is not completely bypassedbefore the HPF circuit 104 is switched into circuit when transitioningfrom the low pass state to the high pass state, and vice versa. However,by complying with the above operational rule set (or a version with thefirst two steps reversed in order), a “through-path” can be essentiallycreated dynamically, since the sum of the normalized series and shuntreactances is minimized. Such a dynamic “through-path” would correspondto transition state 5 in FIG. 5D.

FIG. 5D is a graph 580 of monotonic phase transition behavior for asimulation of one embodiment of a phase shifter cell 100 havingdynamically switched reactances. Graph line 582 shows that the sum ofthe series reactances (normalized) is controlled so as to monotonicallyincrease while transitioning from a low pass state to a high pass state.Graph line 584 shows that the sum of the shunt reactances (normalized)is controlled so as to monotonically decrease while transitioning fromthe low pass state to the high pass state. Graph line 586 shows that thesum of the normalized series (x/Zo) and shunt reactances (Zo/x) iscontrolled so as to be approximately zero. The opposite transition, fromthe high pass state to the low pass state, will exhibit similar butopposite behavior (e.g., similar to reading the graph 580 fromright-to-left, instead of left-to-right).

The result of using a switched reactance dynamic through-path phaseshifter cell is that, in either transition direction, the phasetransition is monotonic with state, the return loss and insertion lossare kept nearly uniform across all states, and the signal vector rotatesduring the transition. By assuring that the return loss, and mostimportantly, the insertion loss, are kept nearly uniform during thephase state transition, the amplitude of the signal remains unchanged,and thus the phase shifter cell behaves more ideally, having an impactessentially only on phase. Minimizing the impact on signal amplitudewill assure elements downstream from the phase shifter cell will see thesame power level. For example, this will assure that a downstreamamplifier sees a more constant signal level rather than large dips inpower level which could trigger an instability or transient from whichthe signal chain would then need to recover.

Switched Reactance Multi-State Phase Shifter Cell

Some phase shifter cells may be capable of providing a selectable amountof phase shift. One such “multi-state” phase shifter cell is describedin U.S. patent application Ser. No. 15/017,433, filed on Feb. 5, 2016,entitled “Low Loss Multi-State Phase Shifter”. For example, FIGS. 6A-6Care block diagrams of a multi-state phase shifter cell 600 in threedifferent switch states. Referring to FIG. 6A, an RF signal may becoupled to an RF In port to an RF Out port through one or more signalpaths. The signal paths may include a Reference Path (i.e., a “throughpath” with a phase shift of essentially 0°) and/or one or more of NPhase Shifters. In some embodiments, the Reference Path may be omitted,in which case some non-zero amount of phase shift will always be imposedon an applied signal.

A signal path from the RF In port to the RF Out port is selected byconcurrently switching associated switch pairs SWx_(I), SWx_(O) (morecompactly, SWx_(I,O)) under the control of a control circuit (notshown). Each signal path has a signal conduction (active) state when theassociated switch pairs SWx_(I,O) are closed, and has a signal blocking(inactive) state when the associated switch pairs SWx_(I,O) are open.The switch pairs may be implemented as field-effect transistors (FETs)or any suitable switch technology. In the state shown in FIG. 6A, switchpairs SW0 _(I,O) are closed, and thus the RF In port is coupled to theRF Out port through the Reference Path.

One aspect of the present invention to reduce or avoid state-changeglitches uses a “make before break” timing scheme for multi-state phaseshifter cells such as the type shown in FIGS. 6A-6C. In the case ofphase shifter cells having phase shifters all of the same polarity (a“Type 1” configuration, such as 0°, +11.25°, +22.5°, and +33.75°, or−33.75°, −22.5°, −11.25°, and 0°) or which are not directly switchedfrom one polarity to the opposite polarity (a “Type 2” configuration,such as −11.25°, 0°, +11.25°, and +22.5°, or −45°, 0°, +45°, and +90°),as a first step in transitioning from one phase state to another, a nextsignal path is first switched into series connection between the RF Inport and the RF Out port so as to become active, while the previoussignal path remains active—that is, for a period of time, both signalpaths are connected between the RF In port and the RF Out port.Thereafter, the previous signal path is switched out of seriesconnection between the RF In port and the RF Out port, thus becominginactive.

For example, with the starting signal path state shown in FIG. 6A for aType 1 configuration, the RF In port is coupled to the RF Out portthrough the Reference Path. If the next signal path is to be PhaseShifter N, then associated switch pairs SWN_(I,O) are closed whileswitch pairs SW0 _(I,O) remain closed, as shown in FIG. 6B. Thus,momentarily, the RF In port is coupled to the RF Out port through boththe Reference Path and Phase Shifter N. Thereafter, switch pairs SW0_(I,O) are opened, as shown in FIG. 6C, and the RF In port is coupled tothe RF Out port through only Phase Shifter N. This “make before break”or “delayed inactivation” timing scheme may be implemented by openingand closing the associated switches SWx_(I,O) as shown in TABLE 2(bolding indicates a change in switch state).

TABLE 2 Starting Signal Path: Ending Signal Path: Reference Path PhaseShifter N (Switches SW0_(I, O)) (Switches SWN_(I, O)) Initial StateCLOSED OPEN 1^(st) transition CLOSED CLOSED 2^(nd) transition OPENCLOSED

Similarly, if the next signal path after Phase Shifter N is to be PhaseShifter 1, then associated switch pairs SW1 _(I,O) are closed whileswitch pairs SWN_(I,O) remain closed. Thereafter, switch pairs SWN_(I,O)are opened. Accordingly, in both examples, the process “makes” a nextsignal path before the process “breaks” the previous signal path. A Type2 configuration utilizes the same timing scheme as a Type 1configuration, with the added constraint that signal paths are notdirectly switched from one polarity phase shifter to an oppositepolarity phase shifter.

In a variation, an improved way to have a smooth transition of phase forType 1 and 2 configurations of a multi-state phase shifter cell 600 isto transition between all the intermediate phase states in a “step-wise”manner. For example, for a multi-state phase shifter cell 600 havingsignal paths providing −45°, 0°, +45°, and +90° of phase shift (i.e., aType 2 configuration), a three-step transition may be used to switchfrom the −45° state to the +90° state. The phase shifter cell 600 willuse the “make before break” timing scheme described above to switch fromthe −45° state to the 0° state, then switch from the 0° state to the+45° state, and finally switch from the +45° state to the +90° state.The several smaller phase transitions from the initial phase state tothe final phase state change will take a longer time to happen comparedto directly switching from the initial phase state to the final phasestate, but the amplitude of state-change glitches will be significantlyreduced. More particularly, when two of the signal paths are connectedbetween the RF In port and the RF Out port, the phase difference of thecombined signal at the RF Out port is much lower (only 45° in thisexample), reducing signal cancellation at the output. In contrast,moving directly from the −45° state to the +90° state using “make beforebreak” will cause the combining signal at the output to be 135° out ofphase, increasing cancellation and in turn increasing the glitchamplitude.

A timing control circuit for implementing such a “step-wise” timingscheme may be readily implemented using a look-up table or an up/downcounter to control the sequence of switch activations/deactivationsneeded to change from an initial phase shift state to a final selectedphase state in a “step-wise” fashion. For example, FIG. 6D is a blockdiagram of one embodiment of a timing control circuit 620 that may beused to control a multi-state phase shifter cell 600 having four signalpaths in a Type 1 or Type 2 configuration, controlled by control signalsS0-S3, respectively. The previous digital state of the multi-state phaseshifter cell 600—the Latched Digital Input—is provided to the InitialState input of an Up/Down Counter 622, and is used to set the counter tocount from the initial phase state to the final requested phase state.The output of the Up/Down Counter 622 is coupled to a Latch 624 and toone input of a Difference Circuit 626. Coupled to a second input of theDifference Circuit 626 is a final Requested Digital State. Thedifference (negative or positive) between the previous phase state andthe final phase state, output by the Difference Circuit 626 as a CounterDirection signal, will decide the counting direction of the Up/DownCounter 622.

As the Up/Down Counter 622 counts, the difference computed by theDifference Circuit 626 diminishes. Once the A and B inputs are the same,a Clock Gate signal from the Difference Circuit 626 to an AND gate 628goes low and stops the output of a Clock Generator 630 from reaching theUp/Down Counter 622 as the Gated CLK signal, thus stopping counting.

The Gated CLK signal is also used to control the Latch 624. When theGated CLK signal is low, the last count from the Up/Down Counter 622 iscaptured as the Latched Digital Input. When the Gated CLK signal ishigh, the Latch 624 is just a “through pass” gate and couples the countoutput of the Up/Down Counter 622 to a 2:4 Decoder 632, whichselectively activates a set of State Dependent Delay circuits 634 a-634d, which in turn output control signals S0-S3. The states of controlsignals S0-S3 change in a sequential (but overlapping) order asdetermined by the Initial State input, the Requested Digital State, andthe Counter Direction of the Up/Down Counter 622. For example, if theInitial State input is the binary code for the phase state controlled byS1, and the Requested Digital State is the binary code for the phasestate controlled by S3, then the Up/Down Counter 622 will count frombinary “10” to “11”. The corresponding State Dependent Delay circuits634 c-634 d will output S2 and S3 in a “make before break” overlappingsequence to connect corresponding phase shifter signal paths between theRF In port and the RF Out port.

In the case of a multi-state phase shifter cell 600 with Phase Shiftersof opposite polarities in which signal paths may be switched from onepolarity phase shifter to a phase shifter of opposite polarity (e.g.,Phase Shifter N may provide a +90° phase shift, while Phase Shifter 1may provide a −90° phase shift—a “Type 3” configuration), a slightlydifferent “make before break” timing scheme may be used to avoidglitches and to maintain a monotonic switching order. In this case, theteachings of FIG. 3 may be combined with the teachings of FIGS. 6A-6B,requiring a transition to an intermediate “through-path state” whentransitioning from one polarity phase shifter state to an oppositepolarity phase shifter state. Without a transition to an intermediate“through-path state”, if a multi-state phase shifter cell 600transitions from −X degree to +X degree using a “make before break”timing scheme, total cancellation may happen at the output as thesignals from the two path will be out of phase.

For example, assume a starting signal path state as shown in FIG. 6C,with Phase Shifter N series-coupled between the RF In port and the RFOut port and providing a phase shift of +X°. Further assume that thenext signal path state is to be with Shifter 1 series-coupled betweenthe RF In port and the RF Out port and providing a phase shift of −X°.The “make before break with intermediate through-path stage” timingscheme may be implemented by opening and closing the associated switchesSWx_(I,O) as shown in TABLE 3 (bolding indicates a change in switchstate).

TABLE 3 Starting Signal Reference Path Ending Signal Path (+Phase(through path) Path (−Phase Shifter N) (Switches (Switches Shifter 1)(Switches SWN_(I, O)) SW0_(I, O)) SW1_(I, O)) Initial State CLOSED OPENOPEN 1^(st) transition CLOSED CLOSED OPEN 2^(nd) transition OPEN CLOSEDOPEN 3^(rd) transition OPEN CLOSED CLOSED 4^(th) transition OPEN OPENCLOSED

In a variation of the timing scheme of Table 3, the 2^(nd) and 3^(rd)transitions can be done concurrently, since the reference path is activeand provides a shorted signal path from the RF In port to the RF Outport. Such a timing scheme may be implemented by opening and closing theassociated switches SWx_(I,O) as shown in TABLE 4 (bolding indicates achange in switch state).

TABLE 4 Starting Signal Reference Path Ending Signal Path (+Phase(through path) Path (−Phase Shifter N) (Switches (Switches Shifter 1)(Switches SWN_(I, O)) SW0_(I, O)) SW1_(I, O)) Initial State CLOSED OPENOPEN 1^(st) transition CLOSED CLOSED OPEN 2^(nd) transition OPEN CLOSEDCLOSED 3^(rd) transition OPEN OPEN CLOSED

Without the “make before break” timing schemes described above, theremay be a moment in time when the signal paths from the RF In port to theRF Out port may be disconnected, causing a phase and/or amplitude glitchat the RF Out port. Note that the “make before break with intermediatethrough-path stage” timing scheme for a Type 3 configuration of amulti-state phase shifter cell 600 generally should not be used for Type1 or Type 2 configurations, since transitioning to a 0° state in betweenswitching from two positive or two negative phase states will generallycause a phase glitch.

Circuitry for implementing the “make before break” or “delayedinactivation” logic described above, including the “step-wise makebefore break” variation, may be readily implemented by one of ordinaryskill in the art using combinatorial logic or a look-up table toimplement the switching patterns shown in any of TABLES 2-4. Such acircuit may advantageously be implemented in part using state dependentdelay circuits of the type shown in FIG. 4B. In practice, such logiccircuitry should be present after a conventional cell selection decodercircuit, since transistor gate signals need to be delayed rather thanthe digital selection signal applied to the decoder circuit.

For example, FIG. 6E is a block diagram of one embodiment of a timingcontrol circuit 650 that may be used to control a multi-state phaseshifter cell 600 having three signal paths in a Type 3 configuration(e.g., −90°, 0°, and +90° phase shifters), controlled by control signalsS0-S2, respectively. The timing control circuit 650 will generate ashort time window (time window of length “X”) in which the referencesignal path is turned ON by a control signal S1. More specifically, aphase shift control signal V_(C) is coupled to a fixed delay circuit 652which outputs a delayed version, V_(C) _(_) _(Delayed), of V_(C) after aselected delay time of “X”. A reference path control signal logiccircuit 654 receives V_(C) and V_(C) _(_) _(Delayed) and outputs controlsignal S1 for the reference signal path of the example multi-state phaseshifter cell 600 (i.e., 0° phase shift). In this example, S1 can alsoindependently controlled by a separate control signal C, if desired; ifnot used, C is set to a logic low. The phase shift control signal V_(C)is also coupled to a fixed delay circuit 656 which outputs a delayedversion of V_(C) after a delay time of “X1”; that output is coupled tocomplementary state dependent delay circuits 658 a, 658 b, which outputcontrol signals S2 and S0, respectively, after a delay time of “X2”. Inthis example, the state dependent delay circuits 658 a, 658 b generate adelay only when the output of the fixed delay circuit 656 goes “high tolow”, but otherwise may be similar to the circuit shown in FIG. 4B. Thesmall delay “X1” is added to make sure that the S0 and S2 controlsignals do not change state before S1 is turned ON. In general, thedelay time “X” should be set to be greater than delay times X1+X2.

Multiple Coupled Phase Shifter Cells

Another aspect of the present invention to reduce or avoid phasestate-change glitches encompasses arranging the timing of each phaseshifter cell (or “bit”) in a set of multiple coupled phase shifter cellssuch that the individual cells do not all switch (either ON or OFF) atthe same time.

FIG. 7 is block diagram of an enhanced phase shifter cell 702 thatincorporates a control signal generation circuit. The enhanced phaseshifter cell 702 includes a phase shifter circuit 704, which may besimilar to the phase shifter cells shown in FIG. 1 or FIG. 6A, and acontrol signal generation circuit 706, which may be similar to thecircuit of FIG. 4A or a circuit implementing the logic of TABLES 2-4above. A master control signal V_(C) from a control circuit (not shown)sets a phase shift state for the enhanced phase shifter cell 702, andthe control signal generation circuit 706 provides a set of suitablydelayed signals (shown encircled by dashed oval 708) to the phaseshifter circuit 704, as described above. The control signal generationcircuit 706 may impose an optional delay on the action of the mastercontrol signal V_(C), as described above with respect to the cell delaycircuit 402 of FIG. 4A. The control signal generation circuit 706 mayalso include “make before break” functionality described above withrespect to multi-state phase shifter cells.

FIG. 8 is a block diagram of a first embodiment of multiple coupledphase shifter cells that provide a selectable amount of phase shift toan applied signal. In this example, five phase shifter cells 802-810each provide a different amount of selectable phase shift, varying from11.25° to 180°, to a signal applied at an IN port (note that the orderof the phase shifter cells 802-810 may be varied from the order shown).Each phase shifter cell 802-810 may be similar to the enhanced phaseshifter cell 702 shown in FIG. 7, but with different component values toprovide the indicated amount of phase shift (control signal connectionsare omitted for clarity). This particular embodiment is binary coded,such that a 5-bit command word provided by control circuitry (not shown)can select any one of 32 combinations of the phase shifter cells 802-810(from all bypassed to all active). In other embodiments, thermometercoding, hybrid binary/thermometer coding, or other coding schemes may beused.

In the embodiment shown in FIG. 8, each phase shifter cell 802-810 maybe operated in accordance with the timing scheme shown in FIG. 3, toreduce glitches per cell. Further, a control signal generation circuit400, 706 of the types respectively shown in FIG. 4A and FIG. 7 may beadvantageously used to alter the timing of glitches generated by eachphase shifter cell 802-810. For example, a cell delay circuit 402 foreach phase shifter cell 802-810 may be configured with differing amountsof delay per cell, as indicated in FIG. 8 (i.e., phase shifter cell 802has 300 ns of cell delay provided by a cell delay circuit 402, whilephase shifter cell 810 has 900 ns of cell delay).

The amount of delay for activation of each phase shifter cell 802-810may be determined by simulation or measurement of sample circuits, andmay differ due to different settling times for each phase shifter cell;generally, cells providing larger degrees of phase shift require largersettling times. In general, each phase shifter cell will have aswitching delay time distinct from the switching delay time of at leastone other phase shifter cell so as to mitigate transients arising fromselection of a phase shift state.

FIG. 9 is a block diagram of a second embodiment of multiple coupledphase shifter cells that provide a selectable amount of phase shift toan applied signal. In this example, six phase shifter cells 902-912 eachprovide a distinct amount of selectable phase shift, varying from 11.25°to 90°, to a signal applied at an IN port. Again, each phase shiftercell 902-912 may be similar to the enhanced phase shifter cell 702 shownin FIG. 7, but with different component values to provide the indicatedamount of phase shift. Again, a cell delay circuit 402 for each phaseshifter cell 902-912 may be configured with differing amounts of delayper cell, as indicated in FIG. 9.

The embodiment in FIG. 9 uses two 90° phase shifter cells 910, 912 inplace of the single 180° phase shifter cell 810 of FIG. 8. A 90° phaseshifter cell typically produces less of a glitch than a 180° phaseshifter cell. This embodiment may be binary coded (treating the last twophase shifter cells 910, 912 as one unit, but activating the cells atslight offset times to reduce per cell glitches), thermometer coded,hybrid binary/thermometer coded, or coded with some other scheme. Aswith the embodiment of FIG. 8, the amount of delay for activation ofeach phase shifter cell 902-912 may be determined by simulation ormeasurement of sample circuits.

FIG. 10A is a graph 1000 of amplitude glitches versus time for asimulation of the multiple coupled phase shifter cells shown in FIG. 9,for a worst-case scenario. In this example, showing a transition from alow-pass filter (LPF) state to a high-pass filter (HPF) state, when aControl Signal (bottom of graph) changes state, each of the six phaseshifter cells 902-912 in FIG. 9 changes state. However, due to theaction of the cell delay circuit 402 of each phase shifter cell 902-912,the actual switching time for each cell is offset from each other cellas determined by the delay times indicated in FIG. 9. As can be seenfrom the graph 900, spacing out phase shifter cell switching times toprevent all cells from switching at the same moment in time spreads outthe glitch events associated with each state transition. This is incontrast to the prior art, where concurrent switching of all of thephase shifter cell 902-912 would result in a much larger glitch inamplitude occurring at essentially the same time. For example, FIG. 10Bis a graph 1050 of amplitude glitches versus time for a simulation ofmultiple coupled prior art phase shifter cells concurrently switched ina worst-case scenario (note that the vertical dimension has beencompressed compared to FIG. 10A). In one model, with concurrentswitching, the maximum glitch was about 16 dB at time “Z”, taking intoaccount that all phase shifter cells do not have the same switchresponse time and so do not really produce their respective glitches atexactly the same moment in time (hence the spread of switching transientglitches around time “Z”); if all the phase shifter cells did changestate at the same time, then the maximum glitch would be even greaterwith the prior art configuration.

Methods

Another aspect of the invention includes methods for mitigating signaltransients arising from phase state changes. For example, FIG. 11 is aprocess chart 1100 showing a method for mitigating signal transientsarising from phase state changes in a phase shifter cell having at leasttwo phase shift states and a through-path state, including: switchingfrom a first phase shift state to the through-path state beforeswitching to a next phase shift state (STEP 1102); and thereafterswitching from the through-path state to the next phase shift state(STEP 1104).

As another example, FIG. 12 is a process chart 1200 showing a method formitigating signal transients arising from phase state changes in a phaseshifter cell having at least two phase shift states defined by two ormore series reactances and two or more shunt reactances, including:controlling the sum of the series (or shunt) reactances so as toprogress monotonically in a first direction while transitioning from afirst phase shift state to a next phase shift state (STEP 1202);controlling the sum of the shunt (or series) reactances so as toprogress monotonically in a second direction opposite the firstdirection while transitioning from the first phase shift state to thenext phase shift state (STEP 1204); and minimizing the sum of thenormalized series and shunt reactances while transitioning from thefirst phase shift state to the next phase shift state (STEP 1206). Asshould be clear, STEPS 1202 and 1204 can be performed in either order.

As another example, FIG. 13 is a process chart 1300 showing a method formitigating signal transients arising from phase state changes in a phaseshifter cell having at least two series-coupled selectable half-cells,each selectable half-cell having an active phase shifting state and aninactive decoupled state, including: switching a first selectablehalf-cell initially in the active phase shifting state to an inactivestate (STEP 1302); thereafter, setting a next selectable half-cell tothe active phase shifting state (STEP 1304).

As yet another example, FIG. 14 is a process chart 1400 showing a methodfor mitigating signal transients arising from phase state changes in aphase shifter cell including at least two selectable signal paths, eachselectable signal path having an active state and an inactive state,including: for a first selectable signal path that is initially in theactive state, maintaining that signal path in the active state when anext selectable signal path is to be set to the active state (STEP1402); setting the next selectable signal path to the active state (STEP1404); and thereafter setting the first selectable signal path to theinactive state (STEP 1406).

FIG. 15 is a process chart 1500 showing a method for mitigating signaltransients arising from phase state changes in a phase shifter cellincluding at least two selectable signal paths and a selectablereference path, each selectable signal path and the selectable referencepath having an active state and an inactive state, including:maintaining a first selectable signal path initially in the active statein the active state when a next selectable signal path is to be set tothe active state (STEP 1502); setting the selectable reference path tothe active state during the selected period of time and before the nextselectable signal path is set to the active state (STEP 1504); settingthe next selectable signal path to the active state and the firstselectable signal path is set to the inactive state (STEP 1506); andthereafter setting the selectable reference path to the inactive state(STEP 1508).

FIG. 16 is a process chart 1600 showing a method for mitigating signaltransients arising from phase state changes in a plurality ofseries-coupled phase shifter cells, including: configuring each phaseshifter cell to provide at least one selectable phase shift state (STEP1602); and configuring each phase shifter cell with a switching delaytime distinct from the switching delay time of at least one other phaseshifter cell so as to mitigate transients arising from selection of aphase shift state (STEP 1604).

The methods described above may further include steps based on theteachings of this disclosure, such as providing a control signalgeneration circuit configured to delay generating time-delayed controlsignals for a selectable period time, or wherein the first selectablesignal path has an opposite phase shift polarity with respect to thenext selectable signal path.

Fabrication Technologies and Options

Some embodiments that include phase shifter circuits of the typesdescribed above may also include a digitally controlled RF signalattenuator circuit that provides a discrete set of attenuation statesthat are selected by a binary control word, directly or after decoding.In some applications, it may be beneficial or even necessary toindependently control switching of component shunt reactances within aphase shifter cell (e.g., shunt capacitors C_(LPF) and shunt inductorL_(HPF) shown in FIG. 1). For example, in the timing diagram shown inFIGS. 3, S2 and S4 are sequenced virtually together, in a complementaryfashion. From a math perspective, if the two reactances C_(LPF), L_(HPF)controlled by corresponding switches M2 and M4 are sized per idealLPF/HPF values, then their switching can be concurrent orsequential—being in parallel, the combined reactance of C_(LPF) andL_(HPF) is infinite in the ideal case. However, in reality, eachreactance C_(LPF), L_(HPF) has some finite loss, so to minimize totalloss, it generally would be beneficial to disconnect one of thereactances before connecting the other reactance. Accordingly, someembodiments may separate the sequencing times for S2 and S4. Suchindependent control is also generally useful in implementing phaseshifter cells having dynamic switched reactance through-paths.

As should be readily apparent to one of ordinary skill in the art,various embodiments of the invention can be implemented to meet a widevariety of specifications. Unless otherwise noted above, selection ofsuitable component values is a matter of design choice and variousembodiments of the invention may be implemented in any suitable ICtechnology (including but not limited to MOSFET and IGFET structures),or in hybrid or discrete circuit forms. Integrated circuit embodimentsmay be fabricated using any suitable substrates and processes, includingbut not limited to standard bulk silicon, silicon-on-insulator (SOI),silicon-on-sapphire (SOS), GaN HEMT, GaAs pHEMT, and MESFETtechnologies. However, the inventive concepts described above areparticularly useful with an SOI-based fabrication process (includingSOS), and with fabrication processes having similar characteristics.Fabrication in CMOS on SOI or SOS enables low power consumption, theability to withstand high power signals during operation due to FETstacking, good linearity, and high frequency operation (in excess ofabout 10 GHz, and particularly above about 20 GHz). Monolithic ICimplementation is particularly useful since parasitic capacitancesgenerally can be kept low (or at a minimum, kept uniform across allunits, permitting them to be compensated) by careful design.

The term “MOSFET” technically refers to metal-oxide-semiconductors;another synonym for MOSFET is “MISFET”, formetal-insulator-semiconductor FET. However, “MOSFET” has become a commonlabel for most types of insulated-gate FETs (“IGFETs”). Despite that, itis well known that the term “metal” in the names MOSFET and MISFET isnow often a misnomer because the previously metal gate material is nowoften a layer of polysilicon (polycrystalline silicon). Similarly, the“oxide” in the name MOSFET can be a misnomer, as different dielectricmaterials are used with the aim of obtaining strong channels withsmaller applied voltages. Accordingly, the term “MOSFET” as used hereinis not to be read as literally limited to metal-oxide-semiconductors,but instead includes IGFETs in general.

Voltage levels may be adjusted or voltage and/or logic signal polaritiesreversed depending on a particular specification and/or implementingtechnology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletionmode transistor devices). Component voltage, current, and power handlingcapabilities may be adapted as needed, for example, by adjusting devicesizes, serially “stacking” components (particularly FETs) to withstandgreater voltages, and/or using multiple components in parallel to handlegreater currents. Additional circuit components may be added to enhancethe capabilities of the disclosed circuits and/or to provide additionalfunctional without significantly altering the functionality of thedisclosed circuits.

A number of embodiments of the invention have been described. It is tobe understood that various modifications may be made without departingfrom the spirit and scope of the invention. For example, some of thesteps described above may be order independent, and thus can beperformed in an order different from that described. Further, some ofthe steps described above may be optional. Various activities describedwith respect to the methods identified above can be executed inrepetitive, serial, or parallel fashion. It is to be understood that theforegoing description is intended to illustrate and not to limit thescope of the invention, which is defined by the scope of the followingclaims, and that other embodiments are within the scope of the claims.(Note that the parenthetical labels for claim elements are for ease ofreferring to such elements, and do not in themselves indicate aparticular required ordering or enumeration of elements; further, suchlabels may be reused in dependent claims as references to additionalelements without being regarded as starting a conflicting labelingsequence).

What is claimed is:
 1. A phase shifter cell having at least two phaseshift states defined by two or more series reactances and two or moreshunt reactances, wherein when transitioning from a first phase shiftstate to a next phase shift state, the sum of the series reactances iscontrolled so as to progress monotonically in a first direction, the sumof the shunt reactances is controlled so as to progress monotonically ina second direction opposite the first direction, and the sum of thenormalized series and shunt reactances is minimized.
 2. A phase shiftercell having at least two phase shift states and a through-path state,wherein when switching from a first phase shift state to a next phaseshift state, the phase shifter cell is set to the through-path statebefore being set to the next phase shift state.
 3. A phase shifter cellincluding at least two series-coupled selectable half-cells, eachselectable half-cell having an active phase shifting state and aninactive state, wherein when switching from a first selectable half-cellinitially in the active phase shifting state to a next selectablehalf-cell initially in the inactive state, the first selectablehalf-cell is set to the inactive state before the next selectablehalf-cell is set to the active phase shifting state.
 4. A phase shiftercell including: (a) at least two series-coupled selectable half-cells,each selectable half-cell having an active phase shifting state and aninactive state; and (b) a control signal generation circuit coupled tothe selectable half-cells, and configured to be coupled to a mastercontrol signal, for generating a sequence of time-delayed controlsignals for the selectable half-cells such that when switching from afirst selectable half-cell initially in the active phase shifting stateto a next selectable half-cell initially in the inactive state, thefirst selectable half-cell is set to the inactive state before the nextselectable half-cell is set to the active phase shifting state.
 5. Theinvention of claim 4, wherein at least one selectable half-cell has api-type configuration.
 6. The invention of claim 4, wherein at least oneselectable half-cell has a T-type configuration.
 7. The invention ofclaim 4, wherein the control signal generation circuit is configured todelay generating the time-delayed control signals for a selectableperiod time.
 8. A phase shifter cell including at least two selectablesignal paths, each selectable signal path having an active state and aninactive state, wherein a first selectable signal path initially in theactive state remains in the active state for a selected period of timewhen a next selectable signal path is set to the active state, andthereafter the first selectable signal path is set to the inactivestate.
 9. A phase shifter cell including: (a) a phase shifter circuithaving at least two selectable signal paths, each selectable signal pathhaving an active state and an inactive state; and (b) a control signalgeneration circuit coupled to the selectable signal paths of the phaseshifter circuit, and configured to be coupled to a master controlsignal, for generating a sequence of time-delayed control signals forthe selectable signal paths such that when switching from a firstselectable signal path initially in the active state to a nextselectable signal path initially in the inactive state, the firstselectable signal path remains in the active state for a selected periodof time while the next selectable signal path is set to the activestate, and thereafter the first selectable signal path is set to theinactive state.
 10. A phase shifter cell including at least twoselectable signal paths and a selectable reference path, each selectablesignal path and the selectable reference path having an active state andan inactive state, wherein: (a) a first selectable signal path initiallyin the active state remains in the active state for a selected period oftime when a next selectable signal path is to be set to the activestate; (b) the selectable reference path is set to the active stateduring the selected period of time and before the next selectable signalpath is set to the active state; (c) the next selectable signal path isset to the active state and the first selectable signal path is set tothe inactive state; and (d) thereafter the selectable reference path isset to the inactive state.
 11. The invention of claim 10, wherein thefirst selectable signal path has an opposite phase shift polarity withrespect to the next selectable signal path.
 12. A phase shifter cellincluding: (a) a phase shifter circuit having at least two selectablesignal paths and a selectable reference path, each selectable signalpath and the selectable reference path having an active state and aninactive state; and (b) a control signal generation circuit coupled tothe selectable signal paths of the phase shifter circuit, and configuredto be coupled to a master control signal, for generating a sequence oftime-delayed control signals for the selectable signal paths such thatwhen switching from a first selectable signal path initially in theactive state to a next selectable signal path initially in the inactivestate, the first selectable signal path remains in the active state fora selected period of time while the selectable reference path is set tothe active state, and thereafter the next selectable signal path is setto the active state and the first selectable signal path is set to theinactive state, and thereafter the selectable reference path is set tothe inactive state.
 13. A plurality of series-coupled phase shiftercells each providing at least one selectable phase shift state, whereineach phase shifter cell has a switching delay time distinct from theswitching delay time of at least one other phase shifter cell so as tomitigate transients arising from selection of a phase shift state. 14.The invention of claim 13, wherein the at least one selectable phaseshift state of at least one phase shifter cell includes at least twophase shifting states and a through-path state, wherein when switchingfrom a first phase shifting state to a next phase shifting state, the atleast one phase shifter cell is set to the through-path state beforebeing set to the next phase shifting state.
 15. The invention of claim13, wherein at least one phase shifter cell includes at least twoselectable signal paths, each selectable signal path having an activestate and an inactive state, wherein a first selectable signal pathinitially in the active state remains in the active state for a selectedperiod of time when a next selectable signal path is set to the activestate, and thereafter the first selectable signal path is set to theinactive state.
 16. The invention of claim 13, wherein: (a) the at leastone selectable phase shift state of at least one phase shifter cellincludes at least two phase shifting states and a through-path state,wherein when switching from a first phase shifting state to a next phaseshifting state, the at least one phase shifter cell is set to thethrough-path state before being set to the next phase shifting state;and (b) at least one phase shifter cell includes at least two selectablesignal paths, each selectable signal path having an active state and aninactive state, wherein a first selectable signal path initially in theactive state remains in the active state for a selected period of timewhen a next selectable signal path is set to the active state, andthereafter the first selectable signal path is set to the inactivestate.
 17. The invention of claim 13, wherein at least one phase shiftercell includes at least two selectable signal paths and a selectablereference path, each selectable signal path and the selectable referencepath having an active state and an inactive state, wherein: (a) a firstselectable signal path initially in the active state remains in theactive state for a selected period of time when a next selectable signalpath is to be set to the active state; (b) the selectable reference pathis set to the active state during the selected period of time and beforethe next selectable signal path is set to the active state; (c) the nextselectable signal path is set to the active state and the firstselectable signal path is set to the inactive state; and (d) thereafterthe selectable reference path is set to the inactive state.
 18. Theinvention of claim 17, wherein the first selectable signal path has anopposite phase shift polarity with respect to the next selectable signalpath.
 19. A method for mitigating signal transients arising from phasestate changes in a phase shifter cell having at least two phase shiftstates defined by two or more series reactances and two or more shuntreactances, including: (a) controlling the sum of the series reactancesso as to progress monotonically in a first direction while transitioningfrom a first phase shift state to a next phase shift state; (b)controlling the sum of the shunt reactances so as to progressmonotonically in a second direction opposite the first direction whiletransitioning from the first phase shift state to the next phase shiftstate; and (c) minimizing the sum of the normalized series and shuntreactances while transitioning from the first phase shift state to thenext phase shift state.
 20. A method for mitigating signal transientsarising from phase state changes in a phase shifter cell having at leasttwo phase shift states and a through-path state, including: (a)switching from a first phase shift state to the through-path statebefore switching to a next phase shift state; and (b) thereafterswitching from the through-path state to the next phase shift state. 21.A method for mitigating signal transients arising from phase statechanges in a phase shifter cell having at least two series-coupledselectable half-cells, each selectable half-cell having an active phaseshifting state and an inactive state, including: (a) switching a firstselectable half-cell initially in the active phase shifting state to aninactive state; (b) thereafter, setting a next selectable half-cell tothe active phase shifting state.
 22. A method for mitigating signaltransients arising from phase state changes in a phase shifter cellincluding at least two selectable signal paths, each selectable signalpath having an active state and an inactive state, including: (a) for afirst selectable signal path initially in the active state, maintainingthat signal path in the active state when a next selectable signal pathis to be set to the active state; (b) setting the next selectable signalpath to the active state; and (c) thereafter setting the firstselectable signal path to the inactive state.
 23. A method formitigating signal transients arising from phase state changes in a phaseshifter cell including at least two selectable signal paths and aselectable reference path, each selectable signal path and theselectable reference path having an active state and an inactive state,including: (a) for a first selectable signal path initially in theactive state, maintaining that signal path in the active state when anext selectable signal path is to be set to the active state; (b)setting the selectable reference path to the active state during theselected period of time and before the next selectable signal path isset to the active state; (c) setting the next selectable signal path tothe active state and the first selectable signal path is set to theinactive state; and (d) thereafter setting the selectable reference pathto the inactive state.
 24. A method for mitigating signal transientsarising from phase state changes in a plurality of series-coupled phaseshifter cells, including: (a) configuring each phase shifter cell toprovide at least one selectable phase shift state; and (b) configuringeach phase shifter cell with a switching delay time distinct from theswitching delay time of at least one other phase shifter cell so as tomitigate transients arising from selection of a phase shift state.